1. Field of the Invention
The present invention relates to a semiconductor storage apparatus, in particular, peripheral circuits of a bit line sense amplifier, used for general-purpose DRAMs, and embedded DRAMs.
2. Description of the Related Art
Increase in performance is always required for semiconductor memory devices, such as Dynamic Random Access Memory (DRAM), and increase in speed of random access is required. To increase the speed of random access, it is necessary to also increase the speed of precharge of bit lines, and increase the size of transistors for bit line precharge. This has a large influence on reading operation of a bit line sense amplifier, and may cause malfunction. This point is explained below.
FIG. 1 illustrates a structure of a part of a conventional DRAM adopting a shared sense amplifier of the folded bit line scheme, in which a bit line sense amplifier SA is shared between cell arrays provided on left and right sides thereof. FIG. 1 illustrates only a pair of columns on right and left sides. FIG. 2 illustrates an example of a main part of signal waveform in data reading operation in the DRAM of FIG. 1. In FIG. 2, VPP denotes an “H” level potential of a word line, VBLH denotes an “H” level potential of a bit line, VBLL (normally VSS) denotes an “L” level potential of a bit line, VBL (normally VBLH/2) denotes a bit line precharge potential, and VDD denotes a power potential of a peripheral logic circuit.
In the circuit of FIG. 1, when the circuit is in a standby state (bit line precharge period), cell array selection signals MUXL and MUXR are VPP, and cell array selection transistors QSL, /QSL, QSR, and /QSR are in an ON state. Next, when reading operation of the cell array located on the left side of the sense amplifier SA is performed, the potential of the cell array selection signal MUXR is changed to VPP to VSS, and thereby the right cell array is electrically disconnected from the sense amplifier SA, and the left cell array is selected. Then, the potential of a control signal BLPL for precharge/equalizing transistors Q11 to Q13 which precharge a pair of bit lines BLL and /BLL of the selected left cell array is changed from VPP to VSS. Thereby, precharge of the bit lines BLL and /BLL is released. Thereafter, the potential of the word line WLL is changed from VSS to VPP, and data stored in the memory cells of the left cell array is read on the bit lines BLL and /BLL. After a certain time interval, the potential of an NMOS driver transistor activating signal SEN for the sense amplifier SA is changed from VSS to VBLH, and the potential of a PMOS drive transistor activating signal SEP for the sense amplifier SA is changed from VBLH to VSS. Thereby, the data read on the bit lines BLL and /BLL is amplified by the sense amplifier SA, and the potential of the “H” bit line in the bit lines BLL and /BLL is changed to VBLH, and the potential of the “L” bit line is changed to VSS. Thereafter, the potential of a column selection signal CSL of a CSL gate is activated from VSS to VDD, data of a pair of sense amplifier bit lines SBL and /SBL is transferred to a pair of data lines DQ and /DQ, and thereby reading is performed. In reverse to the above, writing is performed by transferring data of the data lines DQ and /DQ to the sense amplifier bit lines SBL and /SBL.
FIG. 3 is a diagram illustrating a signal waveform to explain an influence on reading operation when the size of bit line precharge/equalizing transistors is increased to increase the speed of the random access operation illustrated in FIG. 2. When bit line precharge is stopped, the potential of the bit lines BLL and /BLL directly before the word line WLL is activated is lower than the bit line precharge potential VBL, by the influence of noise which occurs in fall of the bit line precharge signal BLPL. When the size of bit line precharge/equalizing transistors is increased, noise which occurs in fall of the bit line precharge signal BLPL also increases as a matter of course. Therefore, the potential of the bit lines BLL and /BLL directly before the word line WLL is activated remarkably lowers. Thus, the difference in potential generated between the bit lines BLL and /BLL when data “0” of memory cells is read is reduced, and malfunction is caused.
As a measure against the above problem, it is considered to reduce noise which occurs in fall of the bit line precharge signal BLPL illustrated in FIG. 3 by providing rising noise reverse to the above noise. Specifically, as illustrated in FIG. 4, a PMOS transistor QP is connected in parallel with a bit line equalizing transistor Q13 of the cell arrays. Then, when precharge and equalizing of the bit lines are stopped, the PMOS transistor QP is changed from ON state to OFF state by a control signal BLPLa as illustrated in a signal waveform diagram of FIG. 5, and thereby rising noise is provided to the bit lines BLL and /BLL.
However, the above case has the following problem. Specifically, transistors having a thin gate oxide film are used as transistors forming the sense amplifier SA, for the purpose of increasing the operation speed thereof. In comparison with this, transistors having a thick gate oxide film are used as bit line precharge/equalizing transistors, since it is necessary to provide a high voltage not less than “bit line precharge potential VBL+the threshold of the transistors” to them as a gate potential. Further, transistors having a thick gate oxide film are used as cell array selection transistors, since it is necessary to provide a high voltage not less than “bit line high level potential VBLH+the threshold of the transistors” to them as the gate potential, to surely transfer a high level potential of the bit lines. Specifically, since no PMOS transistors having a thick gate oxide film are used in the conventional sense amplifier, if PMOS transistors having a thick gate oxide film are used together as bit line equalizing transistors as measures against noise, it is necessary to newly provide an area for providing the PMOS transistors, and it is feared that the area occupied by the bit line precharge circuit is increased.
Further, if reduction in the operation voltage proceeds, when the bit lines are precharged and equalized, the gate-source potential “VBL-VSS” of the bit line equalizing PMOS transistor QP is lowered. Therefore, it cannot be expected that the bit line equalizing PMOS transistor QP contributes to the bit line equalizing operation, and the bit line equalizing PMOS transistor QP is only used for providing noise to the bit lines. Thus, the efficiency of the transistor QP is very low.
FIGS. 13 and 14 of Jpn. Pat. Appln. KOKAI Pub. No. 2004-87074 disclose a semiconductor integrated circuit apparatus having a memory circuit of the hierarchical bit line scheme, in which increase in operation speed and reduction in power consumption are achieved by a simple structure. In the memory circuit, shared selection MOSFETs are provided between a sense amplifier circuit SA including a CMOS latch circuit and four pairs of complementary bit lines. In response to selection of a word line of any one of first to fourth memory mats, any one of first to fourth selection signals is changed to a selection level, and thereby one of the first to fourth selection switch MOSFETs is changed to ON state. Thereby, any one of first to fourth complementary bit line pairs is connected to a pair of input/output nodes of the sense amplifier, and a signal read from the dynamic memory cells is amplified. In this case, pair of precharge/equalizing MOSFETs which supply precharge voltage to the input/output nodes of the sense amplifier are connected to the input/output nodes during a precharge period. However, the invention disclosed in Jpn. Pat. Appln. KOKAI Pub. No. 2004-87074 does not refer to measures for reducing noise in active operation for cell arrays.